A communications system such as a multi-service router may employ one or more synchronous interfaces such as T1 or E1 interfaces. It is often desirable to exchange data received on one interface with another interface for transfer to an external communications system. In order to make different communication systems synchronous, it may be necessary to transfer clocking information from one communications system to one or more different communications systems using these interfaces. Synchronous data transfer without data loss requires such systems to be synchronized.
Synchronous interfaces may transfer clocking information embedded/encoded in the data itself. Alternatively, synchronous interfaces may use a separate medium to transfer clocking, other than the medium used to transfer data. Examples of such synchronous serial interfaces include those defined by the Electronic Industries Association EIA-530 and EIA-449 standards.
A T1 or E1 interface embeds clocking information in the data stream. A T1/E1 receiver may then recover the clocking information using PLL (phase locked loop) techniques. For example, a T1 line rate clock is 1.544 MHz (Million Hertz) while an E1 line rate clock is 2.048 MHz. A common submultiple of both of these frequencies is 8 kHz (thousand Hertz). Dividing a recovered T1 or E1 line rate clock by 193 or 256, respectively, yields 8 kHz. Thus, in time division multiplexed (TDM) systems, 8 kHz is often used as a convenient frequency to which a system TDM synchronizer locks.
FIG. 1 shows a host system general TDM clocking scheme 10. The host system in one embodiment is a network processing device such as a router, switch, gateway, Private Branch Exchange (PBX), or any other type of device that requires clock synchronization. A TDM synchronizer 12 outputs a 32.768 MHz master clock (CLK—32M) 14 to a TDM clock formatting and distribution subsystem 16. Under system software control, the TDM master clock 14 may free-run according to a local (i.e. internal) frequency reference or it may phase lock to a frequency reference (RSYNC) 18 recovered from an external synchronous interface such as a T1 or E1 lines 20—1–20—N.
One or more T1 or E1 lines 20 may be connected to a Wide Area Network (WAN) 21 that can include Public Switched Telephone Networks (PSTN), Frame Relay, Asynchronous Transfer Mode (ATM) and Internet Protocol (IP) packet switched networks. One or more T1 or E1 lines 25 may also be connected directly to additional host systems 27 including a router, switch gateway or PBX located downstream from host system 10.
In one embodiment, the TDM synchronizer 12 slaves off a clock generated by the WAN 21. In another embodiment, the synchronizer 12 provides the master clock for other devices in WAN 21. The master clock 14 is used by the TDM clock formatting and distribution subsystem 16 to generate, format, and distribute TDM clocking 22 to various synchronous interfaces 24—1–24—N and 26 used for data exchange and for clocking transfer.
The clocking 22 includes the Layer1 clock (L1CLK) and also an associated sync pulse (L1SYNC) that occurs with an 8 kHz frequency used to delimit 125 us (microsecond) long TDM frames. Each L1CLK/L1SYNC pair is delivered to the “back end” of a synchronous interface such as a T1 or E1 Framer/Line Interface Unit (LIU) 24—1–24—N. A CLK/SYNC pair is also delivered to a TDM time/space switch 26 that provides data exchange among the interfaces 24—1–24—N.
FIG. 2 shows in more detail one of the T1/E1 framer/LIUs 24. The receive clock recovery (Rx PLL) block 30 provides clocking for data recovery and also provides RSYNC (recovered 8 kHz) to the host TDM subsystem 16 shown in FIG. 1. The transmit port 32 of the T1/E1 line 20 may optionally be loop timed or internally timed. An internally timed transmit port 32 derives its transmit clock from the L1CLK 34 received from the TDM subsystem 16. A loop timed transmit port 32 derives its transmit clock from a receive clock recovered from receive port 33 via receive clock recovery (RxPLL) block 30.
In either case, the T1/E1 framer exchanges receive data (L1RxD) 38 and transmit data (L1TxD) 40 with the host TDM switch 26 based on CLK—32M 14 using its L1CLK/L1SYNC pair 34/36. Receive data and transmit data are stored in elastic store buffers 42 in the framer 24 and allow for phase deviations between the T1/E1 line interface clocking and the back end CLK—32M based clocking 34/36.
The host TDM clocking system 10 (FIG. 1) can transfer its timing reference via the internally timed T1/E1 interface 24 to another TDM subsystem for example, in another network processing device. The TDM synchronizer in the other network processing device must select the RSYNC derived from its respective T1/E1 framer/LIU 24 as the reference that its system master TDM synchronizer 12 locks. In this manner, a clocking hierarchy may be formed from one system to the next.
FIG. 3 shows in more detail the system master TDM synchronizer 12 in FIG. 1 that uses a digital phase locked loop (DPLL) synchronizer 50 with various features followed by an analog phase locked loop (APLL) 54. The DPLL 50 provides most of the TDM synchronization functions, providing a 16.384 MHz output frequency 56. The DPLL uses a fixed 20 MHz master oscillator (20 MHz TCXO) 52, with high quality frequency accuracy and stability. In one embodiment, the DPLL 56 is a model no. MT9045A manufactured by Zarlink Corporation. Of course, other types of DPLLs can be used. The DPLL 56 is controlled by the host system 10 via control signals 19. The DPLL 50 also provides a DPLL lock detect output 51 indicating to the host system whether its 16.384 MHz output 56 is phase locked to its Ref—in input 18.
The DPLL 50 can accept an 8 kHz input frequency reference (Ref—in) 18, with the capability of phase locking its output Fout—DPLL (16.384 MHz) 56 to Ref—in 18. In one embodiment, the capture and lock range of the DPLL 50 is +/−230 parts per million (ppm) minus the +/−ppm accuracy of the 20 MHz oscillator signal 58. The APLL 54 attenuates inherent jitter from the DPLL 50 while doubling the 16.384 MHz signal 56 to 32.768 MHz. This is a convenient frequency employed for the formatting of TDM interface back-end clocking signals.
The lock range of the APLL 54 may be narrower than that of the DPLL 50, due to dependence upon the parameters of crystal 60, trim capacitors 62 and of the integrated circuitry inside APLL 54. For example, crystal frequency parameters may be affected by process variation, temperature and aging.
PLLs used for synchronization and timing recovery have practical design limitations. One such limitation is frequency capture and lock range. T1 and E1 standards mandate lock range requirements based on clocking stratum hierarchy. The widest lock range is required of the Stratum 4 hierarchical level. For T1 circuits, this requirement is +/−32 ppm relative to its nominal line rate while that for E1 is +/−50 ppm.
Good jitter performance, crystal based, analog PLLs used in TDM synchronization circuits typically have lock ranges limited by several factors such as the “pullability” of the frequency of the crystal oscillator circuit. Furthermore, crystal aging, temperature, and initial tolerance as well as trim frequency offset variations and accuracy of the trim capacitors in the APLL 54 affect its center frequency as well as its maximum-to-minimum frequency lock range.
These combined effects yield a typical lock range for the APLL 54 that is significantly narrower than that of the DPLL 50. Hence, the APLL 54 dominates the overall synchronization lock range. Due to the lock range variability of the APLL 54 resulting from component and environmental variations, it is necessary to test the clocking scheme during manufacture to guarantee lock range specifications are met.
To confirm the lock range requirement is met, the system master TDM synchronizer 12 must be tested for its ability to lock input frequency references that span the desired +/−ppm lock range, with some guard banding factored in. This requires not only accurate input reference frequency synthesis, but also requires circuitry to confirm the output frequency (Fout)14 of the master TDM synchronizer 12 (FIG. 1) is locked to its reference input (Ref—in) 18.